Verilog CASE statement example with State Machine

//An example of verilog case statement

module caseExample( input wire clock, input wire resetn, output reg [1:0] state);

`define S0  2'd0
`define S1  2'd1
`define S2  2'd2

reg [1:0] state_nxt;

always @(posedge clock or negedge resetn) 
         if(!resetn) state <= `S0;
         else state <= state_nxt;


always@(*) begin
state_nxt = state;
case(state)
     `S0:                    state_nxt = `S1;
     `S1:                    state_nxt = `S2;
     `S2:                    state_nxt = `S0;
     default:              state_nxt = `S0;
endcase
end

endmodule