An Example of Verilog Sync RAM

// Verilog RTL Port SRAM
// Synch. RAM 32x256
// INTEL MICRO CORP
module DPRAM (
              input wire       mem_clk,   // RTL RAM clock
 input wire [7:0] wrAddr,
 input wire [31:0] dprIn,
 input wire dprWe,  // Write enable
 input wire [7:0] rdAddr,
 output reg [31:0] dprOut
                    );
reg [31:0] memArray [0:255];
always @ (posedge mem_clk) begin
if(dprWe) memArray[wrAddr] <= dprIn;
dprOut <= memArray[rdAddr];
end
endmodule