Monday, August 22, 2016

Note About Using Verilog Task and Functions

Tasks & Functions

  • Both tasks and functions are defined locally in the module in which the tasks and functions will be invoked. 
  • No initial or always statement may be defined within either tasks or functions.
  • Tasks and functions are different — task may have 0 or more arguments of type input, output or inout ; function must have at least one input argument. 
  • Tasks do not return value but pass values through output and inout arguments; functions always return a single value, but cannot have output or inout arguments. 
  • Tasks may contain delay, event or timing control statements; functions may not. 
  • Tasks can invoke other tasks and functions; functions can only invoke other functions, but not tasks.


module TestTop;
 reg [1:0] r1;
 reg [3:0] r2;
 reg r3;

 initial begin
 r1 = 2'b01;
 r2 = myFunc(r1); // Invoke function
 $display("r2 = %b", r2);

 myTask (r2, r3); // Invoke task
 $display("myTask return = %d",r3);

 end

 task myTask;
 input [3:0] i;
 output myTaskOut;
 begin
 #10;
 myTaskOut = (i == 4'b0101);
 end
 endtask

 function [3:0] myFunc;
 input [1:0] i;
 begin
 myFunc = {i,i}; // Return value
 end
 endfunction

endmodule

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