How to use verilog "parameter"

Parameterized Instantiations
The values of parameters can be overridden during instantiation of leave as default.
Or "defparam" statement can be used for the same purpose.

module myGate ( a, b, c, d );
 parameter x = 0;
 input a, b;
 output c, d;
 parameter y = 0, z = 0;
 ...
endmodule
module top;
 reg A, B;
 wire C, D;
 myGate #(2, 4, 3) m1 (A, B, C, D);
// x = 2, y = 4, z = 3 in instance m1
                                                        
 myGate #(5, 3, 1) m2 (.b(B), .d(D), .c(C), .a(A));
// x = 5, y = 3, z = 1 in instance m2        
                                                                 
 defparam m3.x = 4, m3.y = 2, m3.z = 5;
 myGate m3 (A, B, C, D); // x = 4, y = 2, z = 5 in instance m3
 ...
endmodule