How to start your first hardware module

//This is an example of the simple Verilog code
//The input terminal is named i.
//The output terminal is named z.

module myINV( input wire i, output wire z);
             assign z= ~i;
endmodule


//TO use the module
//DO:
module tester;
reg insig;
wire outsig;

myINV dut (.i(insig), .z(outsig));

initial begin

$display ("Waveform Dump Enabled. FileName = waves.vcd");
$dumpfile("waves.vcd");
$dumpvars(0,"dut");

insig = 0;
#100;
insig = 1;
#100;
insig = 0;
#100;
$finish;
end

//print output
always @(outsig) $display("outsig = %b @ %d ", outsig, $time);

endmodule