Friday, August 19, 2016

How to start your first hardware module

//This is an example of the simple Verilog code
//The input terminal is named i.
//The output terminal is named z.

module myINV( input wire i, output wire z);
             assign z= ~i;

//TO use the module
module tester;
reg insig;
wire outsig;

myINV dut (.i(insig), .z(outsig));

initial begin

$display ("Waveform Dump Enabled. FileName = waves.vcd");

insig = 0;
insig = 1;
insig = 0;

//print output
always @(outsig) $display("outsig = %b @ %d ", outsig, $time);



  1. You can test he code at .
    Use the online verily simulator. But you need to remove the two $dumpvar functions since the simulator does not support his.

  2. Also SPICE simulation example:

    *CMOS Ring Oscillator example

    V1 vdd 0 5V
    V2 vss 0 0V

    .subckt inv vdd vss in out
    Mp1 vdd in out vdd pch l=0.35u w=20.0u
    Mn1 vss in out vss nch l=0.35u w=10.0u
    Cload out vss 100f

    *5 stage ring
    x1 vdd vss 1 2 inv
    x2 vdd vss 2 3o inv
    x3 vdd vss 3 4 inv
    x4 vdd vss 4 5 inv
    x5 vdd vss 5 1 inv
    rdly 3o 3 1000
    cdly 3 vss 1000f

    .MODEL nch NMOS
    .MODEL pch PMOS

    .TRAN 10p 4n

  3. Also @ you can compile and execute simple java code if you do not know how to install eclipse IDE.