Very simple I2C monitor for digital simulation in Verilog

//System Verilog I2C simulation monitor module 

module i2cMon;

wire SCL = testbench_top.dut.SCLK;

wire SDA = testbench_top.dut.SDA;

integer pattern_cnt;

integer bit_cnt;

reg [7:0] byte_rec;

initial begin

pattern_cnt = 0;

bit_cnt = 0;

end

always @(negedge SDA) begin

    #1;

    if(SCL === 1'b1) begin //START PKT

        bit_cnt =0;

        pattern_cnt = pattern_cnt +1;

        $display ("i2cMon: PKT %d",pattern_cnt );

    end //end START PKT

end

always @(posedge SCL) begin

if(bit_cnt <8) begin

        byte_rec[7-bit_cnt] = SDA;

        bit_cnt = bit_cnt+1;

end

else begin

         $display ("i2cMon: Byte = %h ,ACK = %b", byte_rec, SDA);

         bit_cnt = 0;

    end

end

endmodule